Various digital systems, such as general-purpose computational devices, digital signal processors, video devices, and the like, generally include a processor configured to interpret and process encoded instructions, an attached high-speed memory system. The encoded instructions control the various processing operations of the processor, and are generally stored in selected portions of the memory system, which usually also contains at least a portion of the data to be processed. A memory bus is sometimes present, which serves as a communications channel between the processor and the memory system, so that the encoded instructions and the data may be communicated between the processor and the memory system.
The performance of a digital system may be defined by its speed and efficiency in processing the data. The performance of the digital system therefore includes the speed of the processor in performing arithmetic operations, the adaptability of the digital system to changing user requirements, and other contributing factors. Among these factors is the operating speed of the memory, as well as the availability of the memory for access by the processor.
Another significant performance factor can be the bandwidth supported by the memory bus. The theoretical bandwidth of the bus may be simply estimated by forming the product of the clock rate and the data delivered per clock cycle. For example, if eight bytes are communicated per clock cycle, and the clock rate is 100 MHz, then the theoretical bandwidth of the bus is 0.80 Gigabytes/second. This estimate is based upon full utilization of the bus (e.g., the falling edge of the clock cycle always communicates eight bytes), with no memory latency effects present to decrease the theoretical bandwidth to a somewhat lower sustained bandwidth.
Due to increasing system speeds, bandwidth limitations have become a significant problem. In one known method, the bandwidth of the bus may be increased by increasing the physical width of the bus. As the physical dimensions of integrated circuit devices steadily decrease, however, competition for available “real estate”, or layout space on the device may be strictly limited. In another known method, the bandwidth of the memory bus may be increased by increasing the clock speed of the bus. It is generally understood, however, that limitations also presently exist with regard to increasing the speed of the bus. For example, impedance differences may cause undesired signal reflections within the bus, which adversely affect the overall performance of the system. Further, signal isolation problems may also arise as operational frequencies are further increased.